DELAGE, Eric

Senior System-on-Chip/-FPGA Architect & Design Leader

Embedded system architect with more than 13 years of experience in all aspects of system- on-chip/-fpga architecture and design. Focus on realtime data-streaming computation- intensive applications and rapid platform generation/IP design reuse methodologies. Interested in converting innovative ideas into a profitable business.

My profile is available as Word document in English, en français.

 Photo

Contact Information

Office
Telephone: +33.(0)2.31.29.49.45
Email: eric.delage@zodiac.com
 Home
Telephone: +33.(0)2.31.44.87.69
Email: eric_delage@hotmail.com
My latest contact information is available on Plaxo. You can also reach me via the LinkedIn and Xing networks.

Experience

From 02/2003
Till now
 ZODIAC/IN-SNEC, Development Center of Normandy, France
Telecommunications Business Unit, Hardware Design Group
System-on-FPGA Architect and Design Leader
  • Responsible for the specification, design and verification of multiple system-on-FPGA architectures – ranging from 1Mgates to 12Mgates – for professional wireless communication receivers.
  • Responsible for the specification, design and verification of multiple system-on-FPGA architectures for data-streaming over 300Mb/s TCP and 950Mb/s UDP networks. Study of architectures supporting data transfers through multiple 1Gb/s Ethernet links simultaneously.
  • In-depth study of data-streaming computation-intensive system-on-chip architectures using the concept of network-on-chip with special focus on network switches supporting simultaneously best-effort and guaranteed services.
  • Setup of a FPGA design methodology focusing on rapid processor-based (IBM/PowerPC405) platform generation, IP design reuse and efficient HDL verification.
  • Coaching of several post-graduate trainees (schools: ENSICAEN'08-'06, PARIS VI '05, ENSICAEN '04).
From 07/2002
To 01/2003
 Micronas GmbH, IC Design Center of Freiburg, Germany
Digital Design Group
System-on-Chip Design Leader
  • Responsible for the design and verification of a 100MHz digital signal processor and its integration in a 400Kgates single-processor system-on-chip for portable audio appliances.
  • Participation to several workgroups on the specification of a company-wide IC design process with strong requirement for IP design reuse.
From 07/2000
To 06/2002
 Philips Semiconductors, IC Design Center of Caen, France
Digital Media Business Line, Imaging Group
System-on-Chip Architect
  • Responsible for the specification of an 800Kgates single-processor (ARM946E-S) system-on-chip for digital still-/motion-picture camera (including the choice of its hardware/software partition).
  • Responsible for the specification of several DTL-compliant image & video processing cores.
  • Contribution to the design and verification of a DTL-compliant JPEG compression core.
  • Contribution to the deployment of PHILIPS/DTL point-to-point protocol.
  • Contribution to the deployment of PHILIPS/CoReUse design methodology.
  • Coaching of several junior engineers.
From 01/1999
To 06/2000
 Philips Semiconductors, System Laboratory of Hamburg, Germany
Video Compression and Storage Group
System-on-Chip Architect
  • Responsible for the survey of the digital camera market and the specification of a digital still-/motion-picture camera reference appliance.
  • Contribution to the specification of an 800Kgates two-processor (MIPS/R3000 & MIPS/R1900) system-on-chip for digital still-/motion-picture camera (including the choice of its hardware/software partition).
  • Performance study of MIPS-based system-on-chips including: C modeling of the underlying hardware systems; study of the DIAB compiler, assembler and linker suite; C programming of boot code and benchmarks.
  • Coaching of a post-graduate trainee (ENSERB '99).
From 05/1995
To 12/1998
 Philips Semiconductors, IC Design Center of Caen, France
Digital Media Business Line, Imaging Group
System-on-Chip Design Leader
  • Responsible for the specification, design and verification of the 250Kgates image and video processing sub-system of a single-processor (MIPS/R3000) system-on-chip for 1.3Mpixel digital still-picture camera.
  • Contribution to the development of several ICs for the Imaging market.
  • Coaching of a post-graduate trainee (INSA '98).

Skills

Management
Skills
  • Commitment to insurance quality processes
  • ASIC/FPGA project planning & monitoring
  • Post-graduate trainee & junior engineer coaching
Technical
Skills
  • System-on-Chip/-FPGA architectures for multimedia, telecommunication and networking appliances
  • MIPS/R3000, ARM/ARM946E-S, IBM/PowerPC405 and Freescale/PQ3 processors
  • ARM/AMBA-AXI/-AHB, OCP-IP/OCP, Philips/DTL and IBM/CoreConnect interconnects
  • Network-on-Chip/-FPGA endpoints & switches for on-chip communication
  • Matlab, Simulink and SystemC modeling of complex systems
  • VHDL and Verilog verification with Cadence/NC-Sim and Mentor/ModelSim
  • VHDL and Verilog synthesis with Synopsys/DC-Compiler and Synplicity/Synplify Pro
  • Hardware implementation of image and video processing algorithms
  • Hardware implementation of BPSK/CPFSK demodulation algorithms
  • Hardware implementation of data-streaming solutions over TCP/UDP networks
Language
Skills
  • French (native)
  • English (fluent)
  • German (fluent - daily use)
Several contributions to multi-cultural projects as well as several experiences abroad : 3 months in 1996 in Eindhoven (Holland), 18 months in 1999-2000 in Hamburg (Germany), 7 months in 2002-2003 in Freiburg (Germany) - which were great opportunities to better understand other cultural environments and to learn from their ways of thinking and working.

Graduations

From 09/1989
To 06/1994
 Ecole Supérieure d'Ingénieurs en Electrotechnique et Electronique (E.S.I.E.E), Paris, France
Diplôme d'Ingénieur en Microélectronique reconnu par l'Etat (réussi avec félicitations).
Post-Graduate Degree in Microelectronics (succeeded with honors).
From 09/1993
To 06/1994
 Université Pierre et Marie Curie (U.P.M.C), Paris, France
Diplôme d'Etudes Approfondies en Microélectronique (réussi avec félicitations).
Post-Graduate Degree in Microelectronics (succeeded with honors).

Hobbies

Enjoying the moments spent with my family. Assisting my 3-year and 1-year old sons in discovering and understanding the world. With this experience I developed some competencies in pedagogy and organization.
Cooking with my wife. Reading comics. Listening to music. Watching movies. Meeting friends.
Reading, understanding & learning. I currently focus on projective geometry and vision technology with the objective to develop an innovative System-on-Chip for autonomous vehicle or robot navigation. In the past years I focused on Java programming and plug-in development for the Eclipse RCP platform and the JXTA peer-to-peer technology.